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EM MICROELECTRONIC - MARIN SA
EM6603
Ultra Low Power Multi I/O Microcontroller
Features
* Low Power - typical 1.8A active mode - typical 0.35A standby mode - typical 0.1A sleep mode @ 1.5V, 32kHz, 25 C * Low Voltage - 1.2 to 3.6 V * buzzer - three tone * ROM - 2k x 16 (Mask Programmed) * RAM - 96 x 4 (User Read/Write) * 2 clocks per instruction cycle * RISC architecture * 4 software configurable 4-bit ports * Up to 16 inputs (4 ports) * Up to 12 outputs (3 ports) * Serial (Output) Write buffer - SWB * Voltage level detection * Analogue watchdog * Timer watchdog * 8 bit timer / event counter * Internal interrupt sources (timer, event counter, prescaler, SWB) * External interrupt sources (portA + portC) Figure 1.Architecture
Figure 2.Pin Configuration
Description
The EM6603 is an advanced single chip low cost, mask programmed - CMOS 4-bit microcontroller. It contains ROM, RAM, watchdog timer, oscillation detection circuit, combined timer / event counter, prescaler, voltage level detector and a number of clock functions. Its low voltage and low power operation make it the most suitable controller for battery, stand alone and mobile equipment. The EM66XX series is manufactured using EM Microelectronic's Advanced Low Power CMOS Process.
Typical
* * * * * * * *
Applications
sensor interfaces domestic appliances security systems bicycle computers automotive controls TV & audio remote controls measurement equipment R/F and IR. control
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EM6603 at a glance
* Power Supply - Low Voltage, low power architecture including internal voltage regulator - 1.2V ... 3.6 V battery voltage - 1.8A in active mode - 0.35A in standby mode - 0.1A in sleep mode @ 1.5V, 32kHz, 25 C - 32 kHz Oscillator * RAM - 96 x 4 bit, direct addressable * ROM - 2048 x 16 bit metal mask programmable * CPU - 4 bit RISC architecture - 2 clock cycles per instruction - 72 basic instructions * Main Operating Modes and Resets - Active mode (CPU is running) - Standby mode (CPU in Halt) - Sleep mode (No clock, Reset State) - Initial reset on Power-On (POR) - External reset pin - Watchdog timer (time-out) reset - Oscillation detection watchdog reset - Reset with input combination on PortA (metal option) * 4-Bit Input PortA - Direct input read - Debounced or direct input selectable (reg.) - Interrupt request on input's rising or falling edge, selectable by register. - Pull-down or none, selectable by metal mask - Software test variables for conditional jumps - PA3 input for the event counter - Reset with input combination on PortA (metal option) * 4-Bit Input/Output PortB - separate input or output selection by register - Pull-up, Pull-down or none, selectable by metal mask if used as Input - Buzzer output on PB0 * 4-Bit Input/Output PortC - Input or Output port as a whole port - Debounced or direct input selectable (reg.) - Interrupt request on input's rising or falling edge, selectable by register. - Pull-up, pull-down or none, selectable by metal mask if used as input - CMOS or N-channel open drain mode * 4-Bit Input/Output PortD - Input or Output port as a whole port - Pull-up, Pull-down or none, selectable by metal mask if used as Input - CMOS or N-channel open drain mode - Serial Write Buffer clock and data output * Serial (output) Write Buffer - max. 256 bits long clocked with 16/8/2/1kHz - automatic send mode - interactive send mode : interrupt request when buffer is empty * Buzzer Output - if used output on PB0 - 3 tone buzzer - 1kHz, 2kHz, 2.66kHz
- 32kHz output possible on the STB/RST pin - 15 stage system clock divider down to 1 Hz
- 3 interrupt requests : 1Hz/8Hz/32Hz - Prescaler reset (from 8kHz to 1Hz) * 8-bit Timer / Event Counter - 8-bit auto-reload count-down timer - 6 different clocks from prescaler - or event counter from the PA3 input - parallel load - interrupt request when comes to 00 hex. * Supply Voltage Level Detector - 3 software selectable levels (1.3V, 2.0V, 2.3V or user defined between 1.3V and 3.0V) - Busy flag during measure - Active only on request during measurement to reduce power consumption
* Prescaler
- 8 external interrupt sources: 4 from Port A and 4
from Port C - 3 internal interrupt sources, prescaler, timer and Serial Write Buffer - each interrupt request is individually maskable - interrupt request flag is cleared automatically on register read
* Interrupt Controller
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Table of Contents
1 OPERATING MODES 1.1 STANDBY MODE 1.2 SLEEP MODE 2 POWER SUPPLY 3 RESET 3.1 OSCILLATION DETECTION CIRCUIT 3.2 RESET PIN 3.3 INPUT PORT (PA0..PA3) RESET 3.4 WATCHDOG TIMER RESET 3.5 CPU STATE AFTER RESET 4 OSCILLATOR 4.1 PRESCALER 5 WATCHDOG TIMER 6 INPUT AND OUTPUT PORTS 6.1 PORTA 6.2 PORTA REGISTERS 6.3 PORTB 6.4 PORTB REGISTERS 6.5 PORTC 6.6 PORTC REGISTERS 6.7 PORTD 6.8 PORTD REGISTERS 7 BUZZER 7.1 BUZZER REGISTER 8 TIMER/EVENT COUNTER 8.1 TIMER/COUNTER REGISTERS 9 INTERRUPT CONTROLLER 9.1 INTERRUPT CONTROL REGISTERS 10 10.1 11 11.1 11.2 12 13 14 15 15 16 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 17 18 18.1 18.2 18.3 19 PERIPHERAL MEMORY MAP ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS STANDARD OPERATING CONDITIONS HANDLING PROCEDURES DC CHARACTERISTICS - POWER SUPPLY PINS DC CHARACTERISTICS - INPUT/OUTPUT PINS DC CHARACTERISTICS - SUPPLY VOLTAGE DETECTOR LEVELS OSCILLATOR INPUT TIMING CHARACTERISTICS PAD LOCATION DIAGRAM PACKAGE AND ORDERING INFORMATION ORDERING INFORMATION PACKAGE MARKING CUSTOMER MARKING SPECIFICATION CHANGE SUPPLY VOLTAGE LEVEL DETECTOR (SVLD) SVLD REGISTER SERIAL (OUTPUT) WRITE BUFFER - SWB SWB AUTOMATIC SEND MODE SWB INTERACTIVE SEND MODE STROBE / RESET OUTPUT 5 5 5 5 6 6 6 7 7 7 8 8 8 9 9 10 11 11 12 12 14 14 15 15 16 17 18 18 20 20 21 23 25 26
Table of Figures
Figure 1.Architecture Figure 2.Pin Configuration Figure 3.Typical Configuration Figure 4.Mode Transition diagram Figure 5.System reset generation Figure 6.Port A Figure 7.Port B Figure 8.Port C Figure 9.Port D Figure 10.Timer / Event Counter Figure 11.Interrupt Request generation Figure 12.Serial write buffer Figure 13.Automatic Serial Write Buffer transmission Figure 14.Interactive Serial Write Buffer transmission Figure 15. EM6603 PAD Location Diagram Figure 16. Dimensions of PDIP24 Pack. - Pack. type "A" Figure 17. Dimensions of TSSOP24 Pack. - Pack. type "F" Figure 18. Dimensions of SOP24 Pack. SOIC - Pack. type "B" 1 1 4 5 6 10 11 13 14 16 19 22 23 25 34 34 35 35
Table of Tables
Table 1. Pin Description Table 2.StandBy and Sleep Activities Table 3. PortA Inputs RESET options (metal Hardware option) Table 4. Watchdog-Timer Option (software option) Table 5. Initial Value After RESET Table 6.Prescaler interrupt source Table 7. Prescaler control register - PRESC Table 8.Watchdog register - WD Table 9.Input / Output Ports Overview Table 10.Option register - Option Table 11.PortA input status register - PortA Table 12.PortA Interrupt request register - IRQpA Table 13.PortA interrupt mask register - MportA Table 14.PortB input status register - PortB Table 15.PortB Input/Output control register - CIOportB Table 16.Ports A&C Interrupt Request Table 17.PortC input/output register - PortC Table 18.PortC Interrupt request register - IRQpC Table 19.PortC interrupt mask register - MportC Table 20.PortD Input/Output register - PortD Table 21.Ports control register - CPIOB Table 22.Buzzer frequency selection Table 23.Buzzer control register - BEEP Table 24.Timer Clock Selection Table 25.Timer control register - TimCtr Table 26.LOW Timer Load/Status register -LTimLS (4 low bits) Table 27.HIGH Timer Load/Status register-HTimLS (4 high bits) Table 28.PA3 counter input selection register - PA3cnt Table 29.PA3 counter input selection Table 30.Main Interrupt request register - IntRq (Read Only)* Table 31.register - CIRQD Table 32. SVLD level selection Table 33.SVLD control register - SVLD Table 34.SWB clock selection Table 35.SWB clock selection register - ClkSWB Table 36.PortD status Table 37.SWB buffer register - SWbuff Table 38.SWB Low size register - LowSWB Table 39.SWB High size register - HighSWB Table 40 Input/Output Ports Table 41 PortA RESET option Table 42 SVLD levels 4 5 7 7 7 8 8 8 9 9 10 10 10 11 11 12 12 12 12 14 14 15 15 17 17 17 17 17 17 18 19 20 20 21 21 21 22 22 22 27 27 27
TEST AT EM - ACTIVE SUPPLY CURRENT TEST 26 METAL MASK OPTIONS 27 28 28 30 30 30 30 30 31 32 33 33 34 34 36 36 36 37
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Table 1. Pin Description Pin Number Pin Name 1 port A, 0 2 port A, 1 3 port A, 2 4 port A, 3 5 port B, 0 6 port B, 1 7 port B, 2 8 port B, 3 9 test 10 Qout/osc 1 11 Qin/osc 2 12 Vss 13 STB/RST 14 port C, 0 15 port C, 1 16 port C, 2 17 port C, 3 18 port D, 0 19 port D, 1 20 port D, 2 21 port D, 3 22 reset 23 Vreg 24 Vdd Function input 0 port A input 1 port A input 2 port A input 3 port A input / output 0 port B input / output 1 port B input / output 2 port B input / output 3 port B test input terminal crystal terminal 1 crystal terminal 2 (input) negative power supply terminal strobe / reset status input / output 0 port C input / output 1 port C input / output 2 port C input / output 3 port C input / output 0 port D input / output 1 port D input / output 2 port D input / output 3 port D reset terminal internal voltage regulator positive power supply terminal Remarks interrupt request; interrupt request; interrupt request; interrupt request; buzzer output tvar 1 tvar 2 tvar 3 event counter input
for EM test purpose only (internal pull-down) Can accept trimming capacitor tw. Vss C reset state + port B, C, D write interrupt request interrupt request interrupt request interrupt request SWB Serial Clock Output SWB Serial Data Output
Active high (internal pull-down) Needs typ. 100nF capacitor tw. Vss
Figure 3.Typical Configuration
For Vdd less then 1.4V it is recommended that Vdd is connected directly to Vreg For Vdd>1.8V then the configuration shown in Fig.3 should be used.
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1 Operating modes
Figure 4.Mode Transition diagram The EM6603 has two low power dissipation modes: STANDBY and SLEEP. Figure 4 is a transition diagram for these modes.
1.1
STANDBY Mode
Executing a HALT instruction puts the EM6603 into STANDBY mode. The voltage regulator, oscillator, Watchdog timer, interrupts and timer/event counter are operating. However, the CPU stops since the clock related to instruction execution stops. Registers, RAM, and I/O pins retain their states prior to STANDBY mode. STANDBY is cancelled by a RESET or an Interrupt request if enabled.
Table 2 : shows the state of the EM6603 functions in STANDBY and SLEEP modes. Table 2.StandBy and Sleep Activities FUNCTION STANDBY SLEEP Oscillator Active Stopped Instruction Execution Stopped Stopped Registers and Flags Retained Reset Interrupt Functions Active Stopped RAM Retained Retained Timer/Counter Active Stopped Watchdog Active Stopped I/O pins Active High-Z or Retained Supply VLD Stopped Stopped Reset pin Active Active
1.2
SLEEP MODE
Writing to the SLEEP* bit in the IntRq* register puts the EM6603 in SLEEP mode. The oscillator stops and most functions of the EM6603 are inactive. To be able to write the SLEEP bit, the SLmask bit must first be set to 1. In SLEEP mode only the voltage regulator and RESET input are active. The RAM data integrity is maintained. SLEEP mode may be cancelled only by a RESET at the terminal pin of the EM6603. The RESET must be high for at least 2sec.
Due to the cold start characteristics of the oscillator, waking up from SLEEP mode may take some time to guarantee that the oscillator has started correctly. During this time the circuit is in RESET and the strobe output STB/RST is high. Waking up from SLEEP mode clears the SLEEP flag but not the SLmask bit. By reading SLmask one can therefore determine if the EM6603 was powered up (SLmask = 0), or woken from SLEEP mode (SLmask = 1).
2
Power Supply
The EM6603 is supplied by a single external power supply between Vdd and Vss, the circuit reference being at Vss (ground). A built-in voltage regulator generates Vreg providing regulated voltage for the oscillator and internal logic. Output drivers are supplied directly from the external supply Vdd. A typical connection configuration is shown in Figure 3. For Vdd less then 1.4V it is recommended that Vdd is connected directly to Vreg For Vdd>1.8V then the configuration shown in Fig.3 should be used.
*registers are marked in bold and underlined like *Bits/Flags in registers are marked in bold only like
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IntRq SLEEP
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3 Reset
To initialize the EM6603, a system RESET must be executed. There are four methods of doing this: (1) (2) (3) (4) Initial RESET from the oscillation detection circuit. External RESET from the RESET PIN. External RESET by simultaneous high input to terminals PA0..PA3. (Combinations defined by metal option) Watchdog RESET (software option).
During any of these RESET's the STB/RST output pin is high. Figure 5.System reset generation
3.1
Oscillation detection circuit
At power on, the built-in voltage regulator starts to follow the supply voltage until Vdd becomes higher than Vreg. Since it is Vreg which supplies the oscillator and this needs time to stabilise, Power-On-Reset with the oscillation detection circuit therefore counts the first 32768 oscillator clocks after power-on and holds the system in RESET. The system will consequently remain in RESET for at least one second after power up. After power up the Analogue Watchdog circuit monitors the oscillator. If it stops for any reason other then SLEEP mode, then a RESET is generated and the STB/RST pin is driven high.
3.2
Reset Pin
During active or STANDBY mode the RESET terminal has a debouncer to reject noise and therefore must be active high for at least 2ms or 16ms (CLK = 32kHz) - software selectable by DebCK in CIRQD register. (see Table 31) At power on, or when cancelling SLEEP mode, the debouncer is not active and so RESET must satisfy the filter time constant (typ. 1sec) such that the RESET must be active high for at least 2sec.
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3.3 Input port (PA0..PA3) RESET
With a mask option it is possible to choose from four PortA reset combinations. The selected ports must be simultaneously high for at least 2ms/16ms (CLK = 32kHz) due to the presence of debouncers. Note also, that RESET with port A is not possible during SLEEP mode. Below are the combinations of Port A (PA0..PA3) inputs, which can be used to generate a RESET. They can be selected by metal PortA RESET mask option, described in chapter 14. Table 3. PortA Inputs RESET options (metal Hardware option) Option A Option B Option C Option D Function no inputs RESET RESET = PA0 * PA1 RESET = PA0 * PA1 * PA2 RESET = PA0 * PA1 * PA2 * PA3 Opt. Code RA0 RA1 RA2 RA3
3.4
Watchdog Timer RESET
The Watchdog Timer RESET is a software option and if used it will generate a RESET if it is not cleared. See section 5. Watchdog timer for details. Table 4. Watchdog-Timer Option (software option) Watchdog Function Without Watchdog Time-out reset With Watchdog Time-out reset NoWD bit in Option register 1 0
3.5
CPU State after RESET
RESET initialises the CPU as shown in the Table 5 below. Table 5. Initial Value After RESET name Program counter 0 Program counter 1 Program counter 2 stack pointer index register Carry flag Zero flag HALT Instruction register periphery registers bits 12 12 12 2 7 1 1 1 16 4 symbol PC0 PC1 PC2 SP IX CY Z HALT IR initial value $000 (as a result of Jump 0) undefined undefined SP(0) selected undefined undefined undefined 0 Jump 0 see peripheral memory map
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4 Oscillator
A built-in crystal oscillator circuit generates the system operating clock for the CPU and peripheral circuits from an externally connected crystal (typ. 32.768kHz) and trimmer capacitor (from Qin tw. Vss). The oscillator circuit is supplied by the regulated voltage, Vreg. In SLEEP mode the oscillator is stopped. With Fout bit in PA3cnt register we can put the system 32.768 Hz frequency on STB/RST pin as output.
4.1
Prescaler
Table 6.Prescaler interrupt source Interrupt frequency PSF1 mask(no interrupt) 0 1 Hz 0 8 Hz 1 32 Hz 1 PSF0 0 1 0 1
The input to the prescaler is the system clock signal. The prescaler consists of a fifteen (15) element divider chain which delivers clock signals for the peripheral circuits such as the timer/counter, buzzer, I/O debouncers and edge detectors, as well as generating prescaler interrupts.
The frequency of prescaler interrupts is software selectable, as shown in Table 6. Table 7. Prescaler control register - PRESC Bit 3 2 1 0 Name MTim PRST PSF1 PSF0 Reset 0 0 0 R/W R/W R/W R/W R/W Description Timer/Counter Interrupt Mask Prescaler reset Prescaler Interrupt select 1 Prescaler Interrupt select 0
5
Watchdog timer
If for any reason the CPU crashes, then the watchdog timer can detect this situation and output a system reset signal. This function can be used to detect program overrun. For normal operation the watchdog timer must be reset periodically by software at least once every three seconds (CLK = 32kHz) or a system reset signal is generated to CPU and periphery. The watchdog is active during STANDBY. The watchdog reset function can be deactivated by setting the NoWD bit to 1 in the Option register. In worst case because of prescaler reset function WD time-out can come down to 2 seconds. The watchdog timer is reset by writing 1 to the WDRST bit. Writing 0 to WDRST has no effect. The watchdog timer also operates in STANDBY mode. It is therefore necessary to reset it if this mode continues for more than three seconds. One method of doing this is to use the prescaler 1Hz interrupt such, that the watchdog is reset every second. Table 8.Watchdog register - WD Bit 3 2 1 0 Name WDRST Slmask WD1 WD0 Reset 0 0 R/W R/W R/W R R Description Watchdog timer reset SLEEP mask bit WD Timer data 1/4 Hz WD Timer data 1/2 Hz
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6 INPUT and OUTPUT ports
The EM6603 has four independent 4-bit ports, as shown in Table 9 Table 9.Input / Output Ports Overview Port PA(0:3) Mode Input Mask Options Pull-Up/Down (*)Debouncer (*) + or - IRQ edge RESET combination Nch open drain output Pull-Up/Down on input Pull-Up/Down (*)+ or - IRQ edge (*)Debouncer Nch open drain output Pull-Up/Down on Input Nch open drain output Function(s) Input Interrupt Software Test Variable PA3 input for event counter RESET input(s) Input or Output PB0 for buzzer output Input or Output Port Interrupt Input or Output Port PD0 -SWB serial clock output PD1 -SWB serial data output
PB(0:3) PC(0:3)
Individual input or output Port input or output
PD(0:3)
Port input or Output
(*) Some options can be set also by Option register . Table 10.Option register - Option Bit 3 2 1 0 Name IRQedgeR debPCN debPAN NoWD Reset 0 0 0 0 R/W R/W R/W R/W R/W Description Rising edge interrupt for portA&C PortC without/with debouncer PortA without/with debouncer WatchDog timer Off
IRQedgeR - Valid for both PortA and PortC input interrupt edge. At RESET it is cleared to 0 selecting the falling edge at the input as the interrupt source. When set to 1 the rising edge is active. (option 3 on Fig 6 and Fig 8) debPAN - by default after reset it is 0 enabling the debouncers on whole portA. Writing it to 1 removes the debouncers from the PortA. (option 2 on Figure 6) debPCN - by default after reset it is 0 enabling the debouncers on whole portC. Writing it to 1 removes the debouncers from the PortC. (option 2 on Figure 8) NoWD - by default after reset it is 0 = Watchdog timer is On. Writing it to 1 removes the WatchDog timer.
6.1
PortA
The EM6603 has one four bit general purpose input port. Each of the input port terminals PA3..PA0 has an internal pull-Up/Down resistor which can be selected with mask options. Port information is read directly from the pin into a register. On inputs PA0, PA1, PA2 and PA3 debouncers for noise rejection are added by default. For interrupt generation, one can choose between either direct input or debounced input. With the debPAN bit at 0 in the Option register all the PortA inputs are debounced and with the debPAN bit at 1 none of the PortA inputs are debounced. With the debouncer selected the input must be stable for two rising edges of 1024Hz or 128Hz clocks (at 32kHz). This corresponds to a worst case of 1.95ms or 15.62msec. PortA terminals PA0, PA1 and PA2 are also used as input conditions for conditional software branches as shown on the next page:
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Debounced PA0 is connected to CPU TestVar1 Debounced PA1 is connected to CPU TestVar2 Debounced PA2 is connected to CPU TestVar3 Figure 6.Port A
Additionally, PA3 can also be used as the input terminal for the event counter (see section 8). The input port PA(0:3) also has individually selectable interrupts. Each port has its own interrupt mask bit in the MPortA register. When an interrupt occurs inspection of the IRQpA and the IntRq registers allows the source of the interrupt to be identified. The IRQpA register is automatically cleared by a RESET, by reading the register. Reading IRQpA register also clears the INTPA flag in IntRq register. At initial RESET the MPortA is set to 0, thus disabling any input interrupts. See also section 9 for further details about the interrupt controller.
6.2
PortA registers
Bit 3 2 1 0 Name PA3 PA2 PA1 PA0 Reset R/W R R R R Description PA3 input status PA2 input status PA1 input status PA0 input status
Table 11.PortA input status register - PortA
Table 12.PortA Interrupt request register - IRQpA Bit 3 2 1 0 Name IRQpa3 IRQpa2 IRQpa1 IRQpa0 Reset 0 0 0 0 R/W R R R R Description input PA3 interrupt request flag input PA2 interrupt request flag input PA1 interrupt request flag input PA0 interrupt request flag
Table 13.PortA interrupt mask register - MportA Bit 3 2 1 0 Name MPA3 MPA2 MPA1 MPA0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description interrupt mask for input PA3 interrupt mask for input PA2 interrupt mask for input PA1 interrupt mask for input PA0
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6.3 PortB
The EM6603 has one four bit general purpose I/O port. Each bit PB(0:3) can be separately configured by software to be either input or output by writing to the corresponding bit of the CIOPortB control register. The PortB register is used to read data when in input mode and to write data when in output mode. On each terminal Pull-Up/Down resistor can be selected by metal option which are active only when selected as input. Input mode is set by writing 0 to the corresponding bit in the CIOPortB register. This results in a high impedance state with the status of the pin being read from register PortB. Output mode is set by writing 1 to the corresponding bit in the CIOPortB register. Consequently the output terminal follows the status of the bits in the PortB register. At initial RESET the CIOPortB register is set to 0, thus setting the port to an input. Additionally, PB0 can also be used as a three tone buzzer output. For details see section 7.
6.4
PortB registers
Bit 3 2 1 0 Name PB3 PB2 PB1 PB0 Reset R/W R/W R /W R/W R /W Description PB3 I/O data PB2 I/O data PB1 I/O data PB0 I/O data
Table 14.PortB input status register - PortB
Table 15.PortB Input/Output control register - CIOportB Bit 3 2 1 0 Figure 7.Port B Name CIOPB3 CIOPB2 CIOPB1 CIOPB0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description PB3 Input/Output select PB2 Input/Output select PB1 Input/Output select PB0 Input/Output select
If metal mask option 5Y (Input blocked when Output) is used and the port is declared as the Output (CIOPortB = 1111b) the real port information cannot be read directly. In this case no direct logic operations (like AND PortB) on Output ports are possible. This logic operation can be made with an image of the Port saved in the RAM which we store after on the output port. This is valid for PortB, PortC and PortD when declared as output and the metal Option 5Y is used. In the case of metal option 5N selected direct logic operations on output ports are possible. If metal mask option 6Y (Output Hi-Z in SLEEP mode) the active Output will go Tristate when the circuit goes into SLEEP mode. In the case of 6N output stay active also in the SLEEP mode.
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6.5 PortC
This port can be configured as either input or output (not bitwise selectable). When in input mode it implements the identical interrupt functions as PortA. The PortC register is used to read data when input mode and to write data when in output mode. Input mode is set by writing 0 to the I/O control bit CIOPC in register CPIOB and the input becomes high impedance. On each terminal Pull-Up/Down resistor can be selected by metal option which are active only when selected as input. The output mode is selected by writing 1 to CIOPC bit, and the terminal follows the bits in the PortC register. When PortC is used as an input, interrupt functions as described for PortA can be enabled. Input to the interrupt logic can be direct or via a debounced input. With the debPCN bit at 0 in the Option register all the PortC inputs are debounced and with the debPCN bit at 1 none of the PortC inputs are debounced. MPortC is the interrupt mask register for this port and IRQpC is the portC interrupt request register. See also section 9.
By writing the PA&C bit in the CPIOB data register it is possible to combine PortA and PortC interrupt requests (logic AND) as shown in Table 16.
At initial reset, the CPIOC control register is set to 0, and the port is in input mode. The MPortC register is also set to 0, therefore disabling interrupts.
Table 16.Ports A&C Interrupt Request IRQPA IRQPC PA&C Request to CPU 0 0 X No 0 1 0 Yes 1 0 0 Yes 1 1 0 Yes 0 1 1 No 1 0 1 No 1 1 1 Yes
6.6
PortC registers
Table 17.PortC input/output register - PortC Bit 3 2 1 0 Name PC3 PC2 PC1 PC0 Reset R/W R/W R /W R/W R /W Description PC3 I/O data PC2 I/O data PC1 I/O data PC0 I/O data
Table 18.PortC Interrupt request register - IRQpC Bit 3 2 1 0 Name IRQpc3 IRQpc2 IRQpc1 IRQpc0 Reset 0 0 0 0 R/W R R R R Description input PC3 interrupt request flag input PC2 interrupt request flag input PC1 interrupt request flag input PC0 interrupt request flag
Table 19.PortC interrupt mask register - MportC Bit 3 2 1 0 Name MPC3 MPC2 MPC1 MPC0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description interrupt mask for input PC3 interrupt mask for input PC2 interrupt mask for input PC1 interrupt mask for input PC0
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Figure 8.Port C
For PortC and PortD metal options 5Y/N and 6Y/N are Port-wise (for the whole port). For PortB these options are bit-wise (every terminal can have individual mask set-up for the options 5Y/N and 6Y/N ).
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6.7 PortD
The EM6603 has one all purpose I/O port similar to PortC but without interrupt capability. The PortD register is used to read input data when an input and to write output data for output. The input line can be pulled Up/Down (metal option) when the port is used as input. Input mode is set by writing 0 to the I/O control bit CIOPD in register CPIOB, and the terminal becomes high impedance. On each terminal Pull-Up/Down resistor can be selected by metal option which are active only when selected as input. Output mode is set by writing 1 to the control bit CIOPD. Consequently, the terminal follows the status of the bits in the PortD register. If Serial Write Buffer function is enabled PD0 and PD1 terminals of PortD output serial clock and serial data respectively. For details see 11.0 Serial Write Buffer.
6.8
PortD registers
Bit 3 2 1 0 Name PD3 PD2 PD1 PD0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description PD3 I/O data PD2 I/O data PD1 I/O data PD0 I/O data
Table 20.PortD Input/Output register - PortD
Table 21.Ports control register - CPIOB Bit 3 2 1 0 Figure 9.Port D Name CIOPD CIOPC PA&C Reset 0 0 0 R/W R/W R/W R/W R/W Description not used I/O PortD select I/O PortC select Logical AND of IRQ's from PortA & PortC
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7 BUZZER
The EM6603 has one 50% duty cycle output with three different frequencies which can be used to drive a buzzer. I/O terminal PB0 is used for this function when the buzzer is enabled by setting the BUen bit to 1 . Table 22 below shows how to select the frequency by writing to the BCF1 and BCF0 control flags in the BEEP register. After writing to the buzzer control register BEEP, the chosen frequency (or silence) is selected immediately. With the BUen bit set to 1, the selected frequency is output at PB0. When the BUen is set to 0 PB0 is used as a normal I/O terminal of PortB. The BUen bit has a higher priority over the I/O control bit CIOPB0 in the CIOPortB register.
Table 22.Buzzer frequency selection Tone frequency BCF1 BCF0 silence 1024 Hz 2048 Hz 2667 Hz 0 0 1 1 0 1 0 1
7.1
Buzzer Register
Bit 3 2 1 0 Name TimEn BUen BCF1 BCF0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description Timer/counter enable Buzzer enable Buzzer Frequency control Buzzer Frequency control
Table 23.Buzzer control register - BEEP
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8 Timer/Event Counter
The EM6603 has a built-in 8 bit countdown auto-reload Timer/Event counter that takes an input from either the prescaler or Port PA3. If the Timer/Event counter counts down to $00 the interrupt request flag IntTim is set to 1. If the Timer/Event counter interrupt is enabled by setting the mask flag MTimC set to 1, then an interrupt request is generated to the CPU. See also section 9. If used as an event counter, pulses from the PA3 terminal are input to the event counter. See figure 10 and tables 28 and 29 on the next page for PA3 source selection (debounced or not, Rising/Falling edge). By default rising and debounced PA3 input is selected. The timer control register TimCtr selects the auto-reload function and input clock source. At initial RESET this bit is cleared to 0 selecting no auto-reload. To enable auto-reload TimAuto must be set to 1. The Timer/Event counter can be enabled or disabled by writing to the TIMen control bit in the BEEP register. At initial RESET it is cleared to 0. When used as timer, it is initialised according to the data written into the timer load/status registers LTimLS (low 4 bits) and HTimLS (high four bits). The timer starts to count down as soon as the LTimLS value is written. When loading the Timer/Event counter registers the correct order must be respected: First, write either the control register TimCtr or the high data nibble HTimLS. The last register written should be the low data nibble LTimLS. During count down, the timer can always be reloaded with a new value, but the high four bits will only be accepted during the write of the low four bits. In the case of the auto-reload function, the timer is initialised with the value of the load registers LTimLS and HTimLS. Counting with the auto-reload function is only enabled during the write to the low four bits, (writing TimAuto to 1 does not start the timer counting down with the last value in the timer load registers but it waits until a new LTimLS load). The timer counting to $00 generates a timer interrupt event and reloads the registers before starting to count down again. To stop the timer at any time, a write of $00 can be made to the timer load registers, this sets the TimAuto flag to 0. If the timer is stopped by writing the TimEn bit to 0, the timer status can be read. The current timer status can be always obtained by reading the timer registers LTimLS and HTimLS. For proper operation read ordering should be respected such that the first read should be of the LTimLS register followed by the HTimLS register. Example: To have continuos 1sec timer IRQ with 128Hz one has to write 128dec (80hex) in Timer registers with auto-reload. Using the Timer/Event Counter as the event counter allows several possibilities: 1.) Firstly, load the number of PA3 input edges expected into the load registers and then generate an interrupt request when counter reaches $00. 2.) The second is to write timer/counter to $FF, then select the event counter mode, and lastly enable the event counter by setting the TimEn bit to 1, which starts the count. Because the counter counts down, a binary complement has to be done in order to get the number of events at the PA3 input. 3) Another option is to use the Timer/Event counter in conjunction with the prescaler interrupt, such that it is possible to count the number of the events during two consecutive 32Hz, 8Hz or 1Hz prescaler interrupts. Figure 10.Timer / Event Counter
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Table 24 shows the selection of inputs to the Timer/Event counter. Table 24.Timer Clock Selection TEC2 TEC1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 TEC0 0 1 0 1 0 1 0 1 Timer/Counter clock source not active 2048 Hz from prescaler 512 Hz from prescaler 128 Hz from prescaler 32 Hz from prescaler 8 Hz from prescaler 1 Hz from prescaler PA3 input terminal (see tables 28 and 29)
8.1
Timer/Counter registers
Table 25.Timer control register - TimCtr Bit 3 2 1 0 Name TimAuto TEC2 TEC1 TEC0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description Timer/Counter AUTO reload Timer/Counter mode 2 Timer/Counter mode 1 Timer/Counter mode 0
Table 26.LOW Timer Load/Status register - LTimLS (4 low bits) Bit 3 2 1 0 Name TL3/TS3 TL2/TS2 TL1/TS1 TL0/TS0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description Timer load/status bit 3 Timer load/status bit 2 Timer load/status bit 1 Timer load/status bit 0
Table 27.HIGH Timer Load/Status register - HTimLS (4 high bits) Bit 3 2 1 0 Name TL7/TS7 TL6/TS6 TL5/TS5 TL4/TS4 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description Timer load/status bit 7 Timer load/status bit 6 Timer load/status bit 5 Timer load/status bit 4
Table 28.PA3 counter input selection register - PA3cnt bit 3 2 1 0 Name Fout PA3cntin Reset 0 0 R/W R/W R/W Description empty empty System freq. output on STB/RST pad PA3 input status
Table 29.PA3 counter input selection PA3cntin debPAN 0 X 1 0 1 0 1 1 1 1 X ( Don't care) IRQedgeR X 0 1 0 1 Counter source PA3 debounced rising edge PA3 debounced falling edge PA3 debounced rising edge PA3 not debounced falling edge PA3 not debounced rising edge
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9 Interrupt Controller
The EM6603 has six different interrupt sources, each of which is maskable. These are: External (3) - PortA PA3..PA0 inputs - PortC PC3..PC0 inputs - combined AND of PortA * PortC Internal (3) - Prescaler (32Hz / 8Hz / 1Hz) - Timer/Event counter - SWB in interactive mode For an interrupt to the CPU to be generated, the interrupt request flag must be set (INTxx), and the corresponding mask register bit must be set to 1 (Mxx), the general interrupt enable flag (INTEN) must also be set to 1. The interrupt request can be masked by the corresponding interrupt mask registers MPortx for each input interrupt and by PSF0 ,PSF1 and MTim for internal interrupts. At initial reset the interrupt mask bits are set to 0. INTEN bit is set automatically to 1 by Halt Instruction except when starting the Automatic SWB transfer (see Serial Write Buffer (SWB) chapter 11) The CPU is interrupted when one of the interrupt request flags is set to 1 in register IntRq and the INTEN bit is enabled in the control register CIRQD. INTTE and INTPR flags are cleared automatically after a read of the IntRq register. The other two interrupt flags INTPA (IRQ from PortA) and INTPC (IRQ from PortC) in the IntRq register are cleared only after reading the corresponding Port interrupt request registers IRQpA and IRQpC. At the Power on reset and in SLEEP mode the INTEN bit is also set to 0 therefore not allowing any interrupt requests to the CPU until it is set to 1 by software. Since the CPU has only one interrupt subroutine and because the IntRq register is cleared after reading, the CPU does not miss any of the interrupt requests which come during the interrupt service routine. If any occur during this time a new interrupt will be generated as soon as the CPU comes out of the current interrupt subroutine. Interrupt priority can be controlled through software by deciding which flag in the IntRq register should be serviced first. For SWB interactive mode interrupt see section 11.0 Serial Write Buffer.
9.1
Interrupt control registers
Bit 3 2 1 0 2 Name INTPR INTTE INTPC INTPA SLEEP Reset 0 0 0 0 0 R/W R R R R W* Description Prescaler interrupt request Timer/counter interrupt request PortC Interrupt request PortA Interrupt request SLEEP mode flag
Table 30.Main Interrupt request register - IntRq (Read Only)*
* Write bit 2 only if SLmask=1 If the SLEEP flag is written with 1 then the EM6603 goes immediately into SLEEP mode (SLmask was at 1).
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Table 31.register - CIRQD Bit 3 2 1 0 Name RESERVED RESERVED DebCK INTEN Reset 0 0 R/W R/W R/W Description Debouncer clock select (0=2ms : 1=16ms) Enable interrupt to CPU (1=enabled)
Figure 11.Interrupt Request generation
IRQ mask bit which can be written to 0 or 1 (1 to enable an interrupt) interrupt request flag which is set on the input rising edge.
Timer IRQ flag INTTE and prescaler IRQ flag INTPR arrive independent of their mask bits not to loose any timing information. But the processor will be interrupted only with mask set to 1.
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10 Supply Voltage Level Detector (SVLD)
The EM6603 has a software configurable built-in supply voltage level detector. Three levels can be defined between VDDmin + 100mV and VDDmax - 600mV in steps of 100mV. During SLEEP mode this function is disabled. The required voltage compare level is selected by writing the bits VLC1 and VLC2 in the SVLD control register which also activates the compare measurement. Since the measurement is not immediate the busy flag remains high during the measurement and is automatically cleared low when the measurement is finished. The result is indicated by inspection of the VLDR flag. If the result is 0 then the voltage level is higher than the selected compare level. And if 1 is lower than the compare level. The result VLDR of the last measurement remains until the new one is finished. The new result overwrites the previous one. Table 32. SVLD level selection During the SVLD operation power consumption increases by approximately 3A for 3.9msec. The measurement internally starts with the rising 256Hz edge following the SVLD test command. The additional SVLD consumption stops after the falling edge of the 256Hz internal clock. Table 32 lists the possible voltage levels Evaluation voltage not active VL1 (low level) VL2 VL3 (high level) VLC1 0 0 1 1 VLC0 0 1 0 1
10.1 SVLD register
Table 33.SVLD control register - SVLD Bit 3 2 1 0 Name VLDR busy VLC1 VLC0 Reset 0 0 0 0 R/W R R R/W R/W Description SVLD result (0=higher 1=lower) measurement in progress SVLD level control 1 SVLD level control 0
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11 Serial (Output) Write Buffer - SWB
The EM6603 has a simple Serial Write Buffer (SWB) which outputs serial data and serial clock. The SWB is enabled by setting the bit V03 in the CLKSWB register as well as setting port D to output mode. The combination of the possible PortD mode is shown in Table 34. In SWB mode the serial clock is output on port D0 and the serial data is output on port D1. The signal TestVar[3], which is used by the processor to make conditional jumps, indicates "Transmission finished" in automatic send mode or "SWBbuffer empty" in interactive send mode. In interactive mode, TestVar[3] is equivalent to the interrupt request flags stored in IntRq register : it permits to recognize the interrupt source. (See also the interrupt handling section 9.Interrupt Controller for further information). To serve the "SWBbuffer empty " interrupt request, one only has to make a conditional jump on TestVar[3].
Table 34.SWB clock selection The Serial Write Buffer output clock frequency is selected by bits ClkSWB0 and ClkSWB1 in the ClkSWB register. The possible values are 1kHz (default), 2kHz, 8kHz or 16kHz and are shown in Table 34. SWB clock output 1024 Hz 2048 Hz 8192 Hz 16384 Hz CkSWB1 0 0 1 1 CkSWB0 0 1 0 1
Table 35.SWB clock selection register - ClkSWB Bit 3 2 1 0 Name V03 CkSWB1 CkSWB0 Reset 0 0 0 0 R/W R/W R R/W R/W Description Serial Write buffer selection RESERVED - read 0 SWB clock selector 1 SWB clock selector 0
Table 36.PortD status PortD status CIOPD NORMAL 0 NORMAL 0 NORMAL 1 SWB 1
V03 0 1 0 1
PD0 input input output PD0 serial clock Out
PD1 input input output PD1 SWB serial data
PD2 input input output PD2 output PD2
PD3 input input output PD3 output PD3
When the SWB is enabled by setting the bit V03 TestVar[3], which is used to make conditional jumps, is reassigned to the SWB and indicates either "SWBbuffer empty " interrupt or "Transmission finished" . After Power-on-RESET V03 is cleared at "0" and TestVar[3] is consequently assigned to PA2 input terminal. The SWB data is output on the rising edge of the clock. Consequently, on the receiver side the serial data can be evaluated on falling edge of the serial clock edge.
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Figure 12.Serial write buffer
Table 37.SWB buffer register - SWbuff Bit 3 2 1 0 Name Buff3 Buff2 Buff1 Buff0 Reset 1 1 1 1 R/W R/W R/W R/W R/W Description SWB buffer D3 SWB buffer D2 SWB buffer D1 SWB buffer D0
Table 38.SWB Low size register - LowSWB Bit 3 2 1 0 Name Size[3] Size[2] Size[1] Size[0] Reset 0 0 0 0 R/W R/W R/W R/W R/W Description Auto mode buffer size bit3 Auto mode buffer size bit2 Auto mode buffer size bit1 Auto mode buffer size bit0
Table 39.SWB High size register - HighSWB Bit 3 2 1 0 Name AutoSWB StSWB Size[5] Size[4] Reset 0 0 0 0 R/W R/W R/W R/W R/W Description SWB Automatic mode select SWB start interactive mode Auto mode buffer size bit5 Auto mode buffer size bit4
The SWB has two operational modes, automatic mode and interactive mode.
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11.1 SWB Automatic send mode
Automatic mode enables a buffer on a predefined length to be sent at high transmission speeds ( up to 16khz). In this mode user prepares all the data to be sent (minimum 8 bits, maximum 256 bits) in RAM. The user then selects the clock speed, sets the number of data nibbles to be sent, selects automatic transmission mode (AutoSWB bit set to 1) and enters STANDBY mode by executing a HALT instruction. Once the HALT instruction is activated the SWB peripheral module sends the data in register SWBuff followed by the data in the RAM starting at address 00 up to the address specified by the bits size[5:0] located in the LowSWB, HighSWB registers. During automatic transmission the general INTEN bit is disabled automatically to prevent other Interrupts to reset the standby mode. At the end of automatic transmission EM6603 leaves standby mode and sets TestVar[3] high. TestVar[3] = 1 is signaling SWB transmission is terminated. Once the transmission is finished, do not forget to enable the general INTEN bit if necessary. The data to be sent must be prepared in the following order: First nibble to be sent must be written in the SWBuff register . The other nibbles must be loaded in the RAM from address 0 (second nibble at adr.0, third at adr.1,...) up to the address with last nibble of data to be send = "size" address. Max. address space for SWB is 3E ("size" 3E hex) what gives with SWBuff up to 64 nibbles (256 bits) of possible data to be sent. The minimum possible data length we can send in Automatic SWB mode is 8 bits when the last RAM address to be sent is 00 ("size" = 00) Once data are ready in the RAM and in the SWBuff, user has to load the "size" (adr. of the last nibble to be send - bits size[5:0]) into the LowSWB and HighSWB register together with AutoSWB bit = 1. Now everything is ready for serial transmission. To start the transmission one has to put the EM6603 in standby mode with the HALT instruction. With this serial transmission starts. When transmission is finished the TESTvar[3] (can be used for conditional jumps) becomes active High, the AutoSWB bit is cleared, the processor is leaving the Standby mode and INTEN is switched on.
Figure 13.Automatic Serial Write Buffer transmission
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The processor now starts to execute the first instruction placed after the HALT instruction (for instance write of SWBuff register to clear TESTvar[3]), except if there was a IRQ during the serial transmission. In this case the CPU will go directly in the interrupt routine to serve other interrupt sources. TestVar[3] stays high until SWBuff is rewritten. Before starting a second SWB action this bit must be cleared by performing a dummy write on SWBuff address. Because the data in the RAM are still present one can start transmitting the same data once again only by recharging the SWBuff , LowSWB and HighSWB register together with AutoSWB bit and putting the EM6603 in HALT mode will start new transmission.
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11.2 SWB Interactive send mode
In interactive SWB mode the reloading of the data transmission register SWBbuff is performed by the application program. This means that it is possible to have an unlimited length transmission data stream. However, since the application program is responsible for reloading the data a continuous data stream can only be achieved at 1kHz or 2kHz transmission speeds. For the higher transmission speeds a series of writes must be programmed and the serial output clock will not be continuous. Serial transmission using the interactive mode is detailed in Figure 14. Programming of the SWB in interactive is achieved in the following manner: Select the transmission clock speed using the bits ClkSW0 and ClkSW1 in the ClkSWB register. Load the first nibble of data into the SWB data register SWBbuff Start serial transmission by selecting the bit StSWB in the register HighSWB register. Once the data has been transferred into the serial transmission register a non maskable interrupt (SWBEmpty) is generated and TESTvar[3] goes high. The CPU goes in the interrupt routine, with the JPV3 as first instruction in the routine one can immediately jump to the SWB update routine to load the next nibble to be transmitted into the SWBuff register. If this reload is performed before all the serial data is shifted out then the next nibble is automatically transmitted. This is only possible at the transmission speeds of 1KHz or 2KHz due to the number of instructions required to reload the register. At the higher transmission speeds of 8khz and 16khz the application must restart the serial transmission by writing the StSWB in the High SWBHigh register after writing the next nibble to the SWBbuff register. Each time the SWBuff register is written the "SWBbuffer empty interrupt" and TestVar[3] are cleared to "0". For proper operation the SWBuff register must be written before the serial clock drops to low during sending the last bit (MSB) of the previous data. Figure 14.Interactive Serial Write Buffer transmission
After loading the last nibble in the SWBbuff register a new interrupt is generated when this data is transferred to an intermediate Shift Register. Precaution must be made in this case because the SWB will give repetitive interrupts until the last data is sent out completely and the STSWB bit goes low automatically. One possibility to overcome this is to check in the Interrupt subroutine that the STSWB bit went low before exiting interrupt. Be careful because if STSWB bit is cleared by software transmission is stopped immediately. At the end of transmission a dummy write of SWBuff must be done to clear TESTvar[3] empty interrupt" or the next transmission will not work.
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and "SWBbuffer
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12 STroBe / ReSeT Output
The STB/RST output pin is used to indicate the EM6603 RESET condition as well as write operations to ports B, C and D. For a PortB, PortC and PortD write operation the STROBE signal goes high for half of the system clock period. Write is effected on falling edge of the strobe signal and it can this be used to indicate when data changes at the output port pins. In addition, any EM6603 internal RESET condition is indicated by a continuous high level on STB/RST for the period of the RESET.
13 Test at EM - Active Supply Current test
For this purpose, five instructions at the end of the ROM will be added.
Testloop:
STI LDR NXORX JPZ JMP
00H, 0AH 1BH Testloop 00H
To stay in the testloop, these values must be written in the corresponding addresses before jumping in the loop: 1BH: 32H: 6EH: 6FH: 0101b 1010b 0010b 0011b
Free space after last instruction: JMP 00H (0000) Remark: empty space within the program are filled with NOP (FOFF).
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14 Metal Mask Options
The following options can be selected at the time of programming the metal mask ROM. Table 40 Input/Output Ports
Pull-Up Yes / No Pull-Down Yes / No Nch-open drain Yes / No Input blocked when Output Yes / No Output Hi-Z in SLEEP mode Yes / No
0
1
4
5
*1
6
*2
A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3 D0 D1 D2 D3
PA0 input PA1 input PA2 input PA3 input PB0 In/Out PB1 In/Out PB2 In/Out PB3 In/Out PC0 In/Out PC1 In/Out PC2 In/Out PC3 In/Out PD0 In/Out PD1 In/Out PD2 In/Out PD3 In/Out
Put one letter (Y, N, R, F)in each BOX from proposed for the column. *1 Port wise for PortC and PortD (one possibility for the whole port); PortB bit-wise *2 Port-wise for PortC and PortD (one possibility for the whole port); PortB bit-wise Table 41 PortA RESET option - One Option must be selected
NO PortA reset combination PA0 & PA1 logic AND input reset PA0 & PA1 & PA2 logic AND input reset PA0 & PA1 & PA2 & PA3 logic AND input reset
0
1
2
3
RA PortA RESET
Table 42 SVLD levels - See 16.6 DC characteristics -SV Detector Levels - Write typ. value of used levels
typ. VL1 level [V]
VL SVLD level in Volts
typ. VL2 level [V]
typ. VL3 level [V]
Software name is :
______________.bin, dated ______________
The customer should specify the required options at the time of ordering. A copy of this sheet, as well as the Software ROM characteristic file generated by the assembler (*.STA) should be attached to the order.
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15 PERIPHERAL MEMORY MAP
The following table shows the peripheral memory map of the EM6603. The address space is between $00 and $7F (Hex). Any addresses not shown can be considered to be reserved.
Register name
add add hex dec
power up value b'3210
xxxx
write_bits
read_bits
Remarks
Read/Write_bits
0: D0 1: D1 2: D2 3: D3 0: TS0 1: TS1 2: TS2 3: TS3 0: TS4 1: TS5 2: TS6 3: TS7 0: TEC0 1: TEC1 2: TEC2 3: TimAuto 0: NoWD 1: debPAN 2: debPCN 3:IRQedgeR 0: PA3cntin 1: Fout 2: 3: 0: CkSWB0 1: CkSWB1 2: 3: V03 0: Buff0 1: Buff1 2: Buff2 3: Buff3 0: size[0] 1: size[1] 2: size[2] 3: size[3] 0: size[4] 1: size[5] 2: StSWB 3:AutoSWB 0: VLC0 1: VLC1 2: busy 3: VLDR 0: INTEN 1: DebCK 2: 3: direct addressing
RAM
005f
0-95
LTimLS
60
96
0000
HTimLS
61
97
0000
0: TL0 1: TL1 2: TL2 3: TL3 0: TL4 1: TL5 2: TL6 3: TL7
low nibble of 8bit timer load and status register high nibble of 8bit timer load and status register timer control register with frequency selector option register
TimCtr
62
98
0000
Option
63
99
0000
PA3cnt
65
101
xxx0
PA3 counter input Frequency output on STRB Clock selector for SWB
ClkSWB
68
104
0000
SWBuff
69
105
1111
SWB intermediate buffer
LowSWB
6A
106
0000
low nibble to define the size of data to be send in Automatic mode the size of the data to be sent & SWB control voltage level detector control global interrupt enable debouncer clock internally used for INDEX register internally used for INDEX register
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HighSWB
6B
107
0000
SVLD
6C
108
0000
0: VLC0 1: VLC1 2: 3: -
CIRQD
6D
109
xx00
Index LOW Index HIGH
6E 6F
110 111
xxxx xxxx
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Register name add hex add dec power up value b'3210 0000 write_bits read_bits Remarks Read/Write_bits 0: INTPA 1: INTPC 2: INTTE 3: INTPR 0: WD0 1: WD1 2: SLmask 3: 0 0: PA0 1: PA1 2: PA2 3: PA3 0: IRQpa0 1: IRQpa1 2: IRQpa2 3: IRQpa3 0: MPA0 1: MPA1 2: MPA2 3: MPA3 0: PB0 1: PB1 2: PB2 3: PB3 0: CIOPB0 1: CIOPB1 2: CIOPB2 3: CIOPB3 0: PC0 1: PC1 2: PC2 3: PC3 0: IRQpc0 1: IRQpc1 2: IRQpc2 3: IRQpc3 0: MPC0 1: MPC1 2: MPC2 3: MPC3 0: PD0 1: PD1 2: PD2 3: PD3 0: PA&C 1: CIOPC 2: CIOPD 3: 0: PSF0 0: PSF0 1: PSF1 1: PSF1 2: PRST 2: 0 3: MTim 3: MTim 0: BCF0 1: BCF1 2: BUen 3: TimEn -------
IntRq
70
112
WD
71
113
0000
0: 1: 2: SLEEP 3: 0: 1: 2: SLmask 3: WDrst
interrupt requests sleep mode WatchDog timer control and SLEEP mask Port A status
PortA
72
114
xxxx
IRQpA
73
115
0000
Port A interrupt request
MPortA
74
116
0000
Port A mask
PortB
75
117
xxxx
Port B Input/Output
CIOportB
76
118
0000
Port B Input/Output individual control Port C Input/Output
PortC
77
119
xxxx
IRQpC
78
120
0000
Port C interrupt request
MPortC
79
121
0000
Port C mask
PortD
7A
122
xxxx
Port D Input/Output
CPIOB
7C
124
x000
PortAirq AND PortCirq PortC In/Out PortD In/Out Prescaler control timer mask Buzzer control Timer Enable reserved
PRESC
7D
125
0000
BEEP
7E
126
0000
RegTestEM
7F
127
----
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16 Electrical specifications 16.1 Absolute maximum ratings
min. Supply voltage VDD-VSS Input voltage Storage temperature - 0.2 VSS - 0.2 - 40 max. + 3.6 VDD+0.2 + 125 unit V V C
Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified electrical characteristics may affect device reliability or cause malfunction.
16.2 Standard Operating Conditions
Parameter
Temperature VDD_range1 VSS CVreg fq Rqs CL df/f
value
-20C...+85C +1.4 ...+3.6V 0 V (reference) min. 100nF 32768 Hz 35 kOhm 8.2pF +/- 30 ppm
Description
With internal voltage regulator Without internal voltage regulator regulated voltage capacitor tow. Vss nominal frequency typical quartz serial resistor typical quartz load capacitance quartz frequency tolerance
VDD_range2 (Vreg = VDD) * +1.2 ...+1.8V
16.3 Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range.
16.4 DC characteristics - Power Supply Pins
Vdd=Vreg=1.5V, T=25C (note4) (unless otherwise specified) Parameter ACTIVE Supply Current ACTIVE Supply Current (in active mode) STANDBY Supply Current STANDBY Supply Current (in Halt mode) SLEEP Supply Current SLEEP Supply Current (SLEEP =1) POR voltage RAM data retention Regulated Voltage Vreg not at Vdd Conditions +25C (note2) (note2) (note2) -20C...+85C +25C (note3) -20C...+85C +25C (note3) -20C...+85C Symb. IVDDa IVDDa IVDDh IVDDh IVDDs IVDDs VPOR Vrd Vreg 1.1 1.1 1.5 Min. Typ. (note1) 1.8 Max. 3.0 4.5 0.6 1.8 0.2 1.2 1.1 Unit A A A A A A V V V
0.35
0.1
0.7
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Vdd=3.0V, T=25C (note4) (unless otherwise specified), Vreg not shorted to Vdd Parameter ACTIVE Supply Current ACTIVE Supply Current (in active mode) STANDBY Supply Current STANDBY Supply Current (in Halt mode) SLEEP Supply Current SLEEP Supply Current (SLEEP =1) Regulated Voltage Conditions +25C (note2) (note2) (note3) -20C...+85C +25C (note3) -20C...+85C +25C (note3) -20C...+85C -20C...+85C Symb. IVDDa IVDDa IVDDh IVDDh IVDDs IVDDs Vreg Min. Typ. (note1) 1.8 Max. 3.0 4.5 1.0 1.8 0.4 1.2 1.85 Unit A A A A A A V
0.35
0.1
1.1
* Because of the voltage regulator drop at low voltages Vreg = Vdd when Vdd<1.4V Note1: For current measurement typical quartz described in Operating Conditions is used. All I/O pins without internal Pull Up/Down are pulled to Vdd externally. Note2: Test loop with successive writing and reading of two different addresses with an inverted values (five instructions should be reserved for this measurement), Note3: NOT tested if delivered in chip form. Note4: Test conditions for ACTIVE and STANDBY Supply current mode are: Qin = external square wave, from rail to rail of Vreg (regulated voltage) with 100nF capacitor on Vreg. fQin = 33kHz.
IDD Run M ode; Regulator ; VDD=3.0V 750 [nA] 600 2000 450 1750 1500 -20 0 20 40 60 [C] 300 80 -20 0 20 40 60 [C] IDD Halt M ode; Regulator; VDD=3.0V
2500 [nA] 2250
80
16.5 DC characteristics - Input/Output Pins
Vdd=1.5V / 3.0V, -20C 31
Typ.
Max. 0.3VDD 0.3VDD 0.3VDD 0.3Vreg VDD VDD VDD Vreg
Unit V V V V V V V V mA A mA mA mA
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Pin at hi-impedance
VIH
VOL = 0.3V, VDD = 1.5V
IOL 2.0 800 13.0 1.35 1.50
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Vdd=1.5V / 3.0V, -20C Note 5: Qout is used only with quartz
16.6 DC characteristics - Supply Voltage Detector Levels
T= +25C (unless otherwise specified) 1.3V < VL1 < VL2 < VL3 < 3.0V (VL1 > 1.3V, VL2 > 1.8V, VL3 > 2.0V) Parameter Supply Voltage Detector SVLD lev3 SVLD lev2 SVLD lev1 Supply Voltage Detector SVLD lev3 SVLD lev2 SVLD lev1 SVLD current consumption when activated Conditions Symb. VL3 VL2 VL1 0C...+65C VL3 VL2 VL1 1.5VISVLD
SVLD typical level values must be selected with a precision of 100 mV.
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16.7 Oscillator
1.2V1.2V Vdd>1.2V Vdd>1.5V & Vdd<3.0V Conditions 15 - 35 C 1,4 - 1,6 V Symb. Df / f * DT Df /f * DU CQin CQout RQin/Qout Gm Ustart tdosc tdsys fOD 5,6 12,1 5 2.5 1,2 1.5 2.5 4.0 10 11 12 7 14 10 15.0 Min. Typ. Max. 0,3 ppm 5 ppm 10.0 20.0 Unit 1/C 1/V pF pF M A/V V s s kHz
16.8 Input Timing characteristics
1.5VtRESsl
tdeb0 tdeb0 tdeb1 tdeb1
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17 Pad Location Diagram
Figure 15. EM6603 PAD Location Diagram
nbP v[SVT v[N nbN v[OVUU nbO v[VWO naQ v[POVP
All dimensions in Microns
w[PQVN nbQ w[POSS pcqcr w[OVQU teNU w[OSRN tbb w[OPVT w[POUP
naP w[POUQ naO w[OWOW naN w[OTTS qrMpqr w[OROO
EM6603
afgn>qgxc>ai>v>[>QNRV>aaCeeci>Ao>w>[>PSWN>aaCeeci ee>>v>[>OPN>aaai>>Ao>>w>[>ONP>aaai aNaia>eO>iaN>EaN>>x>[>OO>aaai qsqrp_rc>eO>iaN>bgc>ai>Ai>tqq>?
tqq w[OOQU miCgc w[WPO
n_N w[VUP n_O w[TNV n_P w[QRR n_Q w[VN w[N w[KPON
v[KPNW
miCmii w[PVW rcqr w[ONV
nQ v[PPUT
v[PTQN
18 Package and Ordering Information
Figure 16. Dimensions of PDIP24 Package
nN v[VQW
P-DIP24 .300 INCH body width
v[PVQW
nP v[OWRS
nO v[OPPQ
v[N
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EM6603
Figure 17. Dimensions of TSSOP24 Package
TSSOP24 (0.65mm pitch, 4.4mm body width)
Figure 18. Dimensions of SOP24 Package SOIC
SOP-24(1.27mm pitch, 300mils body width)
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18.1 Ordering Information
Packaged Device: EM6603 %%% SO24 B
Customer Version: customer-specific number given by EM Microelectronic Package: SO24 = 24 pin SOIC TP24 = 24 pin TSSOP DL24 = 24 pin DIP (note 1) Delivery Form: A = Stick B = Tape&Reel (for SO24 and TP24 only)
Device in DIE Form: EM6603 %%% WS 11
Customer Version: customer-specific number given by EM Microelectronic Die form: WW = Wafer WS = Sawn Wafer/Frame WP = Waffle Pack Thickness: 11 = 11 mils (280um), by default 27 = 27 mils (686um), not backlapped (for other thickness, contact EM)
Note 1: Please contact EM Microelectronic-Marin S.A. for availability of DIP package. Ordering Part Number (selected examples)
Part Number Package/Die Form Delivery Form/ Thickness Stick Tape&Reel Tape&Reel 11 mils 11 mils
EM6603%%%SO24A EM6603%%%SO24B EM6603%%%TP24B EM6603%%%WS11 EM6603%%%WP11
24 pin SOIC 24 pin SOIC 24 pin TSSOP Sawn wafer Die in waffle pack
Please make sure to give the complete Part Number when ordering, including the 3-digit version. The version is made of 3 digits %%%: the first one is a letter and the last two are numbers, e.g. P01 , P12, etc.
18.2 Package Marking
DIP and SOIC marking: First line: Second line: Third line: EM6603 0 %%Y PPPPPPPPPPP CCCCCCCCCCC TSSOP marking: EM66 0 3 %% PPPPPPPP CCCCYP
Where: %% = last two-digits of the customer-specific number given by EM (e.g. 05, 12, etc.) Y = Year of assembly PP...P = Production identification (date & lot number) of EM Microelectronic CC...C = Customer specific package marking on third line, selected by customer
18.3 Customer Marking
There are 11 digits available for customer marking on PDIP24 and SO24. There are 4 digits available for customer marking on TSSOP24. Please specify below the desired customer marking.
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SPECIFICATION change date Chapter Version (page) 9/11/99 ver.2.2 All 27/6/97 B/151 All 27/6/97 B/151 All 27/6/97 B/151 (1,2) 16.4(30,31) 27/6/97 B/151 (4) 2 (5) 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 6 (9) 6.4 (11) 6.6 (13) 8 (16) 8 (16) 8.1 (17) PA3 input terminal old text new text New specifications (paper format only) B/151 new version in Doc Control typical 1.8A active mode typical 0.35A standby mode For Vdd less then 1.4V it is recommended that Vdd is connected directly to Vreg For Vdd>1.8V then the configuration shown in Fig.3 should be used. Table 10 option register - Option new table and text describing option register below Figure 7. PortB new explanation of mask options below Figure 8. PortC new explanation of mask options First paragraph changed due to new counter feature added - PA3 clk source (debounced or not, Rising/Falling) PA3 input terminal (see tables 28 and 29) added in Table 24. Timer clock selection Table 28 PA3 counter input selection - PA3cnt Table 29 PA3 counter input selection new tables describing PA3cnt register Figure 10 Timer/Event Counter adapted new description below Figure 11 Interrupt Request generation new formulation and more precise explanation of SVLD (no functional change) Figure 12. Serail write buffer 1024 Hz input added in MUX New explanation of SWB concerning length and IRQ New explanation of SWB in interactive mode New explanation of Metal mask options below Table 40 Input/output Ports Removed (software controlled) New register PA3cnt at address 65 hex VDD_range 1 / +1.4 ..+3.6V VDD_range 2 (Vreg=VDD) / +1.2 ..+1.8V VDD_range 1 / +1.4 ..+3.6V VDD_range 2 (Vreg=VDD) / +1.2 ..+1.8V New way of specifying IOL = f(VOL ,Vdd), IOH = f(VOH ,Vdd), New way of specifying Resistors [k] instead with currents New relative way of specifying SVLD precision and range for 3 levels x% Max CQin 10.0 pf Max CQout 20.0 pf
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Version 2.2 New pagination & new table nb. typical 2.7A active mode typical 0.3A standby mode
27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151 27/6/97 B/151
9.1 (19) 10 (20) 11 (22) 11.1 (23) 11.2 (25) 14 (27) 14 (27) 15 (28) 16.2 (30) 16.2 (30) 16.5 (31) 16.5 (32) 16.6 (32) 16.7 (33) Table 39 Watchdog metal option VDD VDD VOL = f(IOL ,Vdd), VOH = f(IOH ,Vdd), Input Pull-Up/Down resistor expressed by currents Absolute SVLD levels 2.50V, 2.00V, 1.25V Max CQin 8.5 pf Max CQout 15.9 pf
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date Version 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 Chapter (page) All (1) (1) (2) (4) (4) (4) 2 (5) old text B/151 2.0 to 5.5 V Internal interrupt sources (timer, event counter, prescaler) 4 external interrupt sources from PortA For EM test purpose only In Table1 Pin Number 22 In Table1 Pin Number 23 new text C/242 new version in Doc. Control Removed 2.0 to 5.5 V Internal interrupt sources (timer, event counter, prescaler, SWB) 8 external interrupt sources: 4 from PortA and 4 from PortC For EM test purpose only (internal pulldown) Active high (internal pull-down) Needs typ. 100nF capacitor tw. Vss Added at the bottom of the page *registers are marked in bold and underlined like IntRq *Bits/Flags in registers are marked in bold only like SLEEP New register and Bits/Flags marking (see line above) Pull-Up/Down (option 3 on Fig 6 and Fig 8 ) The input line can be pulled Up/Down ( ... Fout / 0 / R/W / System freq. Output on STB/RST pad Added in Table 28. PA3 counter input ... INTTE and INTPR flags are cleared ... New explanation of SWB to be as close as possible to other EM66XX (no functional change) removedColumn 2 & 3 in Table 40 Input/Output Ports ... and notes *3,*4,*5 Fout / Frequency selector on STB/RST Added in Register PA3cnt Max. Supply voltage +3.6V Qin to Qout impedance on PCB min 5 M, typ 10 M New chapter: 17 Pad location diagram. New Figure 15. 18 Package and ordering information New figure 16, 17, 18 18.1 CHIP marking - new description 18.2 CUSTOMER marking - new 18.3 ORDERING information - new 19 Spec Update - new Vreg, VDD SUBSTRATE of the DIE is at VSS 16.4. DC Characteristics - Power Supply Pins - new values for IVDDa, IVDDh, IVDDs Max. + 2 graphs IDDrun = f(T) and IDDhalt = f(T). New testloop 16.4 DC Characteristics - Power Supply Pins - new values for IVDDa, IVDDh, IVDDs Max.
03/02 REV. G/439
27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 27/8/99 C/242 21/6/00 D/295 21/6/00 D/295 21/6/00 D/295
All 6 (9) 6 (9) 6.7 (14) 8.1 (17) 9 (18) 11. (23:25) 14 (27) 15 (28) 16.1 (30) 16.7 (33) 17 (34) 18 (34,35) 18.1 (36) 18.2 (36) 18.3 (36) 19 (37,38) 34 34 16 (30,31) Max. Supply voltage +5.5V Column 2 & 3 in Table 40 Input/Output Ports IntTim and INTPR flags are cleared .. Pull-down (option 2 on Fig 6 and Fig 8 ) The input line can be pulled down ( ...
17 Package and ordering information
VddCA, Vbat (in Figure 15.) (in Figure 15.) IVDDa, IVDDh, IVDDs Max. over temperature change in 16.4 DC characteristics. IVDDa, IVDDh, IVDDs Max. over temperature change in 16.4 DC characteristics.
19.09.01 E/374 13 (26) 19.09.01 E/374 16.4 (30)
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date Version 01/11/01 E/374 11/02/02 F/374 22/03/02 G/439 Chapter (page) All 24 34 & 36 old text new text Change heater & footer Add URL. INTEN must be re-enable after auto SWB Modify pad location diagram & chip marking.
03/02 REV. G/439
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